On the Node Complexity of TGCs with Sub-linear Fan-ins
نویسنده
چکیده
This paper discusses size-optimal solutions for implementing arbitrary Boolean functions using threshold gates. After presenting the state-of-the-art, we start from the result of Horne and Hush [12], which shows that threshold gate circuits restricted to fan-in 2 can implement arbitrary Boolean functions, but require O(2/n) gates in 2n layers. This result will be generalized to arbitrary fan-ins (∆), lowering the depth to n/log∆ + n/∆, and proving that all the (relative) minimums of size are obtained for sub-linear fan-ins (∆ < n − logn). The fact that size-optimal solutions have sub-linear fan-ins is encouraging, as the area and the delay of VLSI implementations are related to the fan-in of the gates.
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